007_index

00 Chapter 6 Active-Recall Diagnostic Quiz

Nakib Noor3 min read

📋 Note Properties
UNLISTEDtrue

00 Chapter 6 Active-Recall Diagnostic Quiz (Registers & Counters)

Test your conceptual understanding and exam readiness for registers, shift registers, ripple counters, synchronous counters, and specialized counters.

Question 1: Parallel Load Register Operation

In a 4-bit register with parallel load control (Load), what is the Boolean input equation Di for each D flip-flop stage?

Solution:

Di = Load · Ii + Load’ · Ai

When Load=1, Di = Ii (new data loaded). When Load=0, Di = Ai (present output held).

Question 2: Serial vs. Parallel Data Transfer Trade-off

Compare Serial Transfer vs. Parallel Transfer in terms of hardware wire count and clock cycles required.

Solution:

  • Serial Transfer: Requires 1 transmission line and N clock cycles to transfer an N-bit word (slow, low hardware cost).
  • Parallel Transfer: Requires N transmission lines and 1 clock cycle to transfer an N-bit word (fast, high hardware cost).

Question 3: Ripple Counter Clock Propagation

Why is an asynchronous counter called a “ripple” counter?

Solution:

Only the LSB flip-flop receives the external system clock. Each subsequent flip-flop is clocked by the output transition of the preceding flip-flop, causing state changes to ripple sequentially down the cascade like a wave.

Question 4: Maximum Frequency Formula for Ripple Counters

Write the formula for the maximum operating clock frequency f_max of an N-bit ripple counter with propagation delay t_pd per flip-flop.

Solution:

f_max = 1 / t_total = 1 / (N · t_pd)

Question 5: Truncated Decade Counter Reset Logic

In a 4-bit binary ripple counter (Q3 Q2 Q1 Q0), what NAND gate logic must be connected to the active-LOW CLR’ pins to construct a Decade (MOD-10) counter?

Solution:

Decode state 10_10 = 1010_2 (Q3=1, Q1=1):

CLR’ = (Q3 · Q1)’

Momentary entry into state 1010 causes CLR’ = 0, resetting all flip-flops immediately to 0000.

Question 6: Asynchronous vs. Synchronous Delay Advantage

Why do synchronous counters operate at much higher maximum clock frequencies than ripple counters for large N?

Solution:

In a synchronous counter, all flip-flops are clocked simultaneously by the master clock, making total delay fixed (t_total = t_pd + t_gate) regardless of bit count N. In a ripple counter, delay grows linearly with N (t_total = N · t_pd).

Question 7: Ring Counter vs. Johnson Counter State Efficiency

For an N-bit shift register, how many unique timing signals are generated by a Ring Counter vs. a Johnson Counter?

Solution:

  • Ring Counter (N flip-flops): Generates N unique states/timing signals (direct feedback Q_{N-1} → D0).
  • Johnson Counter (N flip-flops): Generates 2N unique states/timing signals (inverted feedback Q_{N-1}’ → D0).

Question 8: Johnson Counter 4-Bit Sequence

List the 8-state binary sequence of a 4-bit Johnson counter starting from 0000.

Solution:

0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000

Question 9: 12-Bit Register Decoding

A 12-bit register holds 100010010111. What decimal values does this represent in BCD and Excess-3?

Solution:

  • BCD: 1000 = 8, 1001 = 9, 0111 = 7 ⇒ 897.
  • Excess-3: Subtract 3 from each nibble: 1000-3 = 5, 1001-3 = 6, 0111-3 = 4 ⇒ 564.

Question 10: Shift Register Tracking

A 4-bit register initially contains 1011. What is the content after 2 right shifts if the serial input stream is 10 (applied LSB first: bit 0 then bit 1)?

Solution:

  • Initial: 1011
  • Shift 1 (input 0): 0101
  • Shift 2 (input 1): 1010
  • Result after 2 shifts: 1010

Graph View