00 Chapter 5 Active-Recall Diagnostic Quiz

00 Chapter 5 Active-Recall Diagnostic Quiz (Sequential Logic)

Test your conceptual understanding and exam readiness before reading the full study notes. Attempt each question mentally or on scrap paper before expanding the solution box.

Question 1: Combinational vs. Sequential Feedback

Why can a combinational circuit never store binary state information?

Solution

A combinational circuit has no memory elements and no feedback path from output to input. Output values are strictly determined by current inputs X(t). Storing state requires a bistable feedback loop where past outputs feed back into the combinational logic.

Question 2: Flip-Flop Memory Property

Why is a flip-flop specifically defined as a “1-bit memory element”?

Solution

A flip-flop is a bistable multivibrator that has two stable operating states (Q=1 or Q=0). Once set into a state by a trigger signal, it remains in that state indefinitely (storing 1 bit of data) as long as power is maintained, until another trigger signal changes its state.

Question 3: Latch vs. Flip-Flop Glitch Sensitivity

Why are latches more susceptible to input noise glitches than edge-triggered flip-flops?

Solution

Latches are level-triggered, meaning their output continually tracks inputs throughout the entire duration that the Enable clock signal remains HIGH. Any noise glitch during this active level propagates to the output. Edge-triggered flip-flops sample inputs strictly at the discrete instant of a clock transition (0 1 or 1 0), ignoring input noise outside this setup/hold window.

Question 4: SR Latch Invalid State

In a NOR-gate SR latch, why is S=1, R=1 considered a forbidden/invalid input condition?

Solution

Applying S=1, R=1 forces both NOR outputs to 0 (Q=0 and Q’=0), violating the fundamental complementary property Q = NOT Q’. When inputs return to 00, the final state is unpredictable because it depends on which NOR gate turns off first (a race condition).

Question 5: JK Refinement Proof

Mathematically prove why the JK flip-flop eliminates the invalid state of the SR flip-flop.

Solution

Substitute J=1, K=1 into the JK characteristic equation Qn+1 = J(NOT Qn) + (NOT K)Qn: Qn+1 = (1)(NOT Qn) + (NOT 1)Qn = NOT Qn + 0 = NOT Qn. The output toggles deterministically to its complement, completely replacing the illegal state.

Question 6: Race-Around Condition Threshold

Under what exact physical condition does the Race-Around Condition occur in a JK flip-flop?

Solution

It occurs in a level-triggered JK flip-flop when J=1, K=1 and the clock pulse width tp is greater than the propagation delay tpd of the logic gates (tp > tpd). The output toggles repeatedly (0 1 0 1 …) during the clock pulse, leaving the final output state uncertain.

Question 7: Master-Slave Inversion Isolation

How does a Master-Slave JK flip-flop prevent race-around without reducing clock pulse width?

Solution

It uses two latches clocked by inverted clock signals (CLK and NOT CLK). During CLK=1, the Master accepts inputs while the Slave is disabled. When CLK falls to 0, the Master shuts off and the Slave updates final output Q. Because output feedback cannot reach the Master while the Slave is updating, toggling occurs at most once per clock pulse.

Question 8: D Flip-Flop Characteristic Equation

Derive the characteristic equation of a D flip-flop starting from the SR characteristic equation Qn+1 = S + (NOT R)Qn.

Solution

Insert S = D and R = NOT D into Qn+1 = S + (NOT R)Qn: Qn+1 = D + NOT (NOT D)Qn = D + D Qn = D(1 + Qn) = D. Therefore, Qn+1 = D.

Question 9: Flip-Flop Conversion Rule

What is the general 4-step procedure for converting a Source Flip-Flop into a Target Flip-Flop?

Solution

1. 1. Construct the Target FF characteristic table (Target Inputs + Qn Qn+1).
2. 2. Append required Source FF excitation inputs for each Qn Qn+1 transition.
3. 3. Minimize Source inputs as functions of Target inputs and Qn using K-maps.

4. Draw the combinational drive logic driving the Source FF terminals.

Question 10: State Reduction Equivalence Condition

What two criteria must be satisfied for two states Si and Sj in a state table to be declared equivalent (Si Sj)?

Solution

For every possible input sequence applied to the circuit, states Si and Sj must: 1. Produce identical output sequences. 2. Transition to identical or equivalent next states.