1. Number Systems and Arithmetic
| Term | Definition | Year of Appearance |
|---|---|---|
| Number System | A mathematical framework that defines how numerical values are represented and manipulated using a specific radix or base (e.g., Decimal, Binary, Octal). | Foundational |
| Digital Code | A specific set of rules assigning discrete binary sequences to represent numbers, characters, or symbols for communication and processing. | Foundational |
| Base Complement | A mathematical operation applied to numbers in a specific base (such as 1’s or 2’s complement in binary) used by digital computers to perform subtraction using strictly addition logic. | Foundational |
2. Digital Codes & Error Detection
| Term | Definition | Year of Appearance |
|---|---|---|
| Self-Complementary Code | A code system where the 9’s complement of a decimal digit is generated simply by taking the bitwise 1’s complement of its binary code assignment (e.g., Excess-3, 2421 code). | 2025, 2023, 2021, 2017 |
| Excess-3 Code | A non-weighted, self-complementary digital code derived by mathematically adding (0011) to the standard Binary Coded Decimal (BCD) equivalent of a digit. | 2025, 2023, 2021 |
| Reflected Code (Gray Code) | A specialized unweighted binary code system in which successive sequential numbers differ in exactly one bit position, eliminating the risk of multi-bit transition errors. | 2017 |
| Error Detection Code | A code system that attaches extra redundant bits (such as a parity bit) to a message to identify if an accidental bit-flip error has occurred during data transmission or storage. | 2017 |
| Error Correcting Code | An advanced code system that utilizes a highly structured matrix of redundant bits to not only detect the presence of an error but mathematically locate and automatically correct the specific flipped bit without requiring retransmission. | 2018 |
| Parity Bit | An extra redundant bit appended to a binary data word to ensure the total number of ‘1’s in the string is either consistently even or consistently odd. | Foundational |
3. Boolean Algebra & Logic Simplification
| Term | Definition | Year of Appearance |
|---|---|---|
| Duality Principle | An algebraic rule stating that every valid Boolean expression remains valid if all AND () operators are interchanged with OR () operators, and all 1s are interchanged with 0s, while keeping the variables unchanged. | 2022, 2019, 2018, 2016, 2015 |
| Canonical Form | A unique, strict Boolean algebraic format where every single product or sum term explicitly contains all the domain variables of the function exactly once, either in complemented or uncomplemented form. | 2024, 2022, 2021, 2016, 2015 |
| Standard Form | A simplified, non-unique Boolean expression written as a sum of products (SOP) or product of sums (POS), where individual terms do not necessarily contain all variables present in the domain. | 2024, 2022, 2021, 2019, 2016, 2015 |
| Positive Logic System | A voltage-to-logic mapping system where the higher physical voltage level represents logic 1 and the lower physical voltage level represents logic 0. | 2016, 2015 |
| Negative Logic System | A voltage-to-logic mapping system where the higher physical voltage level represents logic 0 and the lower physical voltage level represents logic 1. | 2016, 2015 |
| Minterm | A canonical product (AND) term containing all domain variables exactly once, which mathematically evaluates to logic 1 for exactly one unique input combination. | Foundational |
| Maxterm | A canonical sum (OR) term containing all domain variables exactly once, which mathematically evaluates to logic 0 for exactly one unique input combination. | Foundational |
| Prime Implicant | A product term obtained in a K-map or Tabular Method by combining the maximum possible number of adjacent minterms, which cannot be further combined to eliminate any variables. | 2018 |
4. Universal Gates & Advanced Logic Families
| Term | Definition | Year of Appearance |
|---|---|---|
| Universal Gate | A specialized logic gate, specifically NAND or NOR, that possesses the unique capability to implement any other Boolean function (including AND, OR, and NOT) without requiring any other gate types. | 2022, 2021 |
| Fan-out | The maximum number of standard logic gate inputs that a single driving gate’s output can reliably power without causing its output voltage levels to drop below acceptable logic thresholds. | 2025, 2024, 2023, 2021, 2019, 2018, 2016 |
| Propagation Delay | The average time interval required for a signal transition to travel from the input terminal of a logic gate to its corresponding output terminal, dictating the maximum speed of the circuit. | 2025, 2024, 2023, 2021, 2018, 2016 |
| Noise Margin | The maximum amount of external, unwanted noise voltage that can be superimposed on a digital signal without causing the receiving logic gate to misinterpret the logic state. | 2025, 2024, 2023, 2021, 2019, 2018, 2016 |
| Power Dissipation | The total electrical power consumed by a logic gate during its active operation, typically expressed in milliwatts (mW), which is released as thermal heat into the integrated circuit package. | 2024 |
| Current Sourcing | The electrical state where a driver logic gate outputs a HIGH voltage and acts as a current source, pushing current out of its terminal and into the input terminal of the connected load gate. | 2025 |
| Power Distribution | The physical hardware network of power supply and ground lines spanning an integrated circuit, which must be carefully designed to prevent voltage drops during rapid logic switching spikes. | 2021, 2018, 2016 |
| IC Logic Families | Categorized groups of digital integrated circuits (such as TTL or CMOS) that share identical underlying electronic characteristics, manufacturing technology, and logic voltage behaviors. | 2016, 2015 |
5. Combinational Circuit Design
| Term | Definition | Year of Appearance |
|---|---|---|
| Combinational Circuit | A digital logic network whose outputs are determined strictly and instantaneously by the present combination of its inputs, featuring no internal feedback loops or memory elements. | Foundational |
| Multiplexer (MUX) | A combinational Medium Scale Integration (MSI) circuit that acts as a digital switch, selecting binary data from one of input lines and routing it to a single output line based on select control lines. | 2019, 2018 |
| Demultiplexer (DeMUX) | A combinational data distributor circuit that receives information on a single input line and routes it to one of possible output lines based on the configuration of its select control lines. | 2019, 2018 |
| Decoder | A combinational circuit that converts binary information from input lines to a maximum of unique output lines, fundamentally generating every unique minterm of the input variables internally. | 2019, 2018, 2017 |
| PLA (Programmable Logic Array) | The most flexible Programmable Logic Device (PLD) architecture, featuring both a completely programmable AND gate array and a completely programmable OR gate array, allowing for complex shared product terms. | 2025, 2024, 2017 |
| ROM (Read-Only Memory) | A Programmable Logic Device (PLD) consisting of a fixed, unalterable AND array (acting as a standard decoder) coupled with a fully programmable OR array, typically used as an unchangeable look-up table. | Foundational |
6. Sequential Logic Circuits
| Term | Definition | Year of Appearance |
|---|---|---|
| Sequential Circuit | A complex digital circuit that incorporates memory elements and feedback loops, meaning its next operational state depends on both the present inputs and its past historical states. | 2019, 2017 |
| Flip-Flop | A clocked, edge-triggered 1-bit memory element used as the foundational building block of sequential circuits, capable of holding a single binary value (1 or 0) until directed to change by a clock pulse transition. | 2025, 2024, 2023, 2018 |
| State Table | A rigorous tabular representation of a sequential circuit detailing the exact relationship between the present states, external inputs, the resulting next states, and the final outputs. | 2022, 2021, 2016, 2015 |
| State Diagram | A visual flow-chart representation of a sequential circuit utilizing nodes (circles) to represent binary states and directed directional lines (arrows) to represent transitions triggered by varying input conditions. | 2022, 2021, 2016, 2015 |
| State Equation | A calculated Boolean algebraic expression that dictates the precise logical and input conditions required to force a flip-flop to transition to its specified next state. | 2022, 2021, 2016, 2015 |
7. Registers & Counters
| Term | Definition | Year of Appearance |
|---|---|---|
| Register | A sequential hardware component consisting of an array of interconnected flip-flops utilized to load, store, and manipulate a multi-bit binary word synchronously. | 2022 |
| Ripple Counter | An asynchronous counter design where the master clock pulse only triggers the first flip-flop, and the output of each flip-flop is directly used as the clock trigger for the subsequent flip-flop in the chain. | Foundational |
8. Memory & AD/DA Converters
| Term | Definition | Year of Appearance |
|---|---|---|
| Memory Element | A bi-stable electronic component or circuit capable of retaining binary data over time, forming the physical storage mechanism behind RAM, core memory, and logic registers. | 2023, 2022, 2020, 2019, 2018, 2015 |
| Resolution | The smallest incremental analog voltage change that corresponds to a single-step change (the Least Significant Bit) in the digital word of an AD/DA converter. | 2025, 2024 |
| Accuracy | A strict measure defining how closely the actual output of an AD/DA converter matches its theoretical ideal output, heavily dependent on the physical precision of its internal resistors and reference voltages. | 2025, 2024 |
| Settling Time | The precise time duration required for the analog output of a Digital-to-Analog (D/A) converter to mathematically stabilize within a specified error margin after a new digital input is applied. | 2025, 2024 |
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3. Boolean Algebra & Logic Simplification
| Term | Definition | Year of Appearance |
|---|---|---|
| Literal | A single domain variable within a Boolean expression, which may appear in either its true (uncomplemented) or complemented form. | 2018 |
| Don’t-Care Condition | An input state with an unspecified or irrelevant output function value, which can be selectively assigned as 0 or 1 in a K-map to further minimize a Boolean expression. | 2015 |
| Essential Prime Implicant (EPI) | A prime implicant that covers at least one minterm not covered by any other prime implicant, making its inclusion in the final simplified expression mandatory. | Foundational |
4. Universal Gates & Advanced Logic Families
| Term | Definition | Year of Appearance |
|---|---|---|
| Fan-in | The total number of input terminals physically available on a specific logic gate. | Foundational |
5. Combinational Circuit Design
| Term | Definition | Year of Appearance |
|---|---|---|
| Half-Adder | A combinational arithmetic circuit that performs the addition of two binary bits, producing a sum and a carry output. | 2019, 2018, 2015 |
| Full-Adder | A combinational arithmetic circuit that performs the addition of three binary bits (two significant bits and a previous carry), producing a sum and a carry output. | 2021, 2020, 2019, 2018 |
| PAL (Programmable Array Logic) | A Programmable Logic Device (PLD) that features a fully programmable AND array coupled with a fixed, unalterable OR array. | Foundational |
| Incompletely Specified Function | A combinational logic function where certain input combinations are guaranteed never to occur, generating outputs categorized as don’t-care terms. | Foundational |
6. Sequential Logic Circuits
| Term | Definition | Year of Appearance |
|---|---|---|
| Latch | A basic, unclocked memory element that transparently transfers data to its output as long as its enable signal is active, highly susceptible to unpredictable state changes. | Foundational |
| Synchronous Sequential Circuit | A sequential circuit whose behavior and state transitions can only occur at discrete instants of time, strictly regulated by a master clock signal. | Foundational |
| Asynchronous Sequential Circuit | A sequential circuit whose state transitions depend entirely on the order in which its input signals change, capable of transitioning at any instant in time without a master clock. | Foundational |
| Trigger (Edge-Triggering) | The precise mechanism where a flip-flop is commanded to change states strictly during the momentary transition (rising or falling edge) of a clock pulse. | Foundational |
| Excitation Table | A tabular design tool that works backward to specify the exact flip-flop input conditions required to force a transition from a present state to a desired next state. | Foundational |
| Characteristic Equation | An algebraic Boolean expression that defines the next state of a flip-flop strictly as a function of its present state and present inputs. | Foundational |
| Race Around Condition | An unstable hardware phenomenon in basic level-triggered JK flip-flops where the clock pulse remains active longer than the propagation delay, causing the output to continuously toggle back and forth uncontrollably. | Foundational |
7. Registers & Counters
| Term | Definition | Year of Appearance |
|---|---|---|
| Shift Register | A sequential hardware register capable of transferring or shifting its stored binary data left or right one position with each successive clock pulse. | Foundational |