FET mosfet biasing

Related Concepts: FET biasing - 3 types | FET biasing concepts | FET bias part 2 note

Based on Chapter 7 (FET Biasing) and the provided Exam Question Bank, here are the comprehensive, exam-oriented notes for Common-Gate, Depletion-type MOSFET, and Enhancement-type MOSFET biasing.

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FET Biasing (Part 2)

1. Common-Gate Configuration

Definition: A configuration where the Gate is grounded, the input signal is applied to the Source, and the output is taken from the Drain. It is the FET equivalent of the Common-Base BJT configuration.

Circuit Description:

• Gate (G): Grounded directly.
• Source (S): Connected to a resistor $R_S$ and typically a supply voltage $V_{SS}$ (provides bias current).
• Drain (D): Connected to $R_D$ and the positive supply $V_{DD}$.

Key Equations (DC Analysis)

1. Input Loop ($V_{GS}$): Applying KVL to the source loop: $-V_{GS}-I_S{R}_S+V_{SS}=0$ Since $I_S=I_D$: $V_{GS}=V_{SS}-I_D{R}_S$ [Note: This is a linear equation ($y=mx+c$). Plot this line on the transfer curve to find the Q-point].
2. Output Loop ($V_{DS}$): $V_{DS}=V_{DD}+V_{SS}-I_D(R_D+R_S)$
3. Terminal Voltages:
   • $V_D=V_{DD}-I_D{R}_D$
   • $V_S=-V_{SS}+I_D{R}_S$
   • $V_G=0\text{ V}$

Step-by-Step Numerical Method

1. Plot the Transfer Curve: Use Shockley’s equation ($I_D=I_{DSS}(1-V_{GS}/V_P{)}^2$).
2. Plot the Bias Line: Use the equation $V_{GS}=V_{SS}-I_D{R}_S$.
   • Intercept 1: Set $I_D=0\to V_{GS}=V_{SS}$.
   • Intercept 2: Set $V_{GS}=0\to I_D=V_{SS}/R_S$.
3. Find Q-Point: The intersection gives $I_{DQ}$ and $V_{GSQ}$.
4. Calculate Output: Substitute $I_{DQ}$ into the output loop equations.

Exam Trend Analysis (PYQ)

• Relevance: High.
• Common Question Type: Numerical problems asking for $I_D,V_S,V_{DS}$ [Sources 154-160].
• PYQ Reference:
  • 2020 & 2021: Determine operating points for Common Gate configuration (Calculation).
  • Note: Be careful with the polarity of $V_{SS}$. The equation assumes $V_{SS}$ is entered as a magnitude.

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2. Depletion-Type MOSFET Biasing

Definition: A MOSFET constructed with a physical channel that can operate in both Depletion Mode (negative $V_{GS}$) and Enhancement Mode (positive $V_{GS}$).

Working Principle:

• Negative $V_{GS}$: Repels electrons, depleting the channel (reduces $I_D$).
• Positive $V_{GS}$: Attracts electrons, enhancing the channel (increases $I_D$ above $I_{DSS}$).
• Gap: The $Si{O}_2$ layer ensures $I_G=0$ A regardless of polarity.

Key Equations

The DC analysis is identical to JFETs because both use Shockley’s Equation. $I_D=I_{DSS}{\left(1-\frac{V_{GS}}{V_P}\right)}^2$

Step-by-Step Numerical Method

1. Select Method: You can use Fixed-Bias, Self-Bias, or Voltage-Divider Bias steps exactly as used for JFETs.
2. Plotting Difference: When drawing the transfer curve, extend the curve into the positive $V_{GS}$ region (for n-channel).
   • Standard Points: $V_P$, $0.3V_P$, $0$, $0.5|V_P|$ (positive side).
   • Example: If $V_P=-4V$, calculate $I_D$ for $V_{GS}=+1V$ to plot the enhancement region.

Exam Trend Analysis (PYQ)

• Relevance: Medium (Theoretical focus).
• Common Question Type: Comparison and Theory.
• PYQ Reference:
  • 2021, 2019: “Distinguish between depletion type and enhancement type MOSFET.”
  • 2016: “Explain construction and operation of depletion type MOSFET.”

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3. Enhancement-Type MOSFET Biasing

Definition: A MOSFET with no physical channel. Current only flows when $V_{GS}$ exceeds a threshold voltage ($V_T$ or $V_{GS(Th)}$).

Important Condition: Shockley’s Equation is NOT valid. Current Equation: $I_D=k(V_{GS}-V_T{)}^2$ Where constant $k$ is determined by a datasheet coordinate ($I_{D(on)},V_{GS(on)}$): $k=\frac{I_{D(on)}}{(V_{GS(on)}-V_T{)}^2}$

A. Feedback Biasing Arrangement

Circuit Description: A resistor $R_G$ is connected directly from the Drain to the Gate. Working Principle (Stabilization):

• Since $I_G=0$, there is no voltage drop across $R_G$.
• Therefore, $V_G=V_D$ and $V_{GS}=V_{DS}$.
• Feedback: If $I_D$ increases $\to$ $V_{DS}$ decreases (due to $R_D$) $\to$ $V_{GS}$ decreases $\to$ $I_D$ decreases. This stabilizes the Q-point.

Key Equations:

1. Bias Line (KVL): $V_{GS}=V_{DD}-I_D{R}_D$ (Because $V_{GS}=V_{DS}$).
2. Device Equation: $I_D=k(V_{GS}-V_T{)}^2$

Step-by-Step Numerical Method:

1. Calculate $k$: Use given $I_{D(on)}$ and $V_{GS(on)}$.
2. Plot Transfer Curve: Plot $I_D=k(V_{GS}-V_T{)}^2$. (Start at $V_T$, go up).
3. Plot Bias Line: Plot $V_{GS}=V_{DD}-I_D{R}_D$.
   • Intercepts: $(V_{DD},0)$ and $(0,V_{DD}/R_D)$.
4. Find Q-Point: Intersection of the curve and line.

B. Voltage-Divider Biasing

Circuit Description: Standard $R_1,R_2$ divider at the gate. Key Equations:

1. Gate Voltage: $V_G=\frac{R_2{V}_{DD}}{R_1+R_2}$.
2. Input Loop: $V_{GS}=V_G-I_D{R}_S$.
3. Output Loop: $V_{DS}=V_{DD}-I_D(R_S+R_D)$.

Exam Trend Analysis (PYQ)

• Relevance: Medium/High.
• Common Question Type: Construction, Operation, and Calculation.
• PYQ Reference:
  • 2022: “Construct an n-channel enhancement-type MOSFET and explain its basic operation.”
  • 2016: “Differences between enhancement and depletion MOSFET.”

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Summary of Exam-Critical Equations

Configuration	Device Equation (Curve)	Network Equation (Line)
Common-Gate	$I_D=I_{DSS}(1-V_{GS}/V_P{)}^2$	$V_{GS}=V_{SS}-I_D{R}_S$
Depletion MOS	$I_D=I_{DSS}(1-V_{GS}/V_P{)}^2$	Same as JFET (Fixed/Self/Divider)
Enhancement Feedback	$I_D=k(V_{GS}-V_T{)}^2$	$V_{GS}=V_{DD}-I_D{R}_D$
Enhancement Divider	$I_D=k(V_{GS}-V_T{)}^2$	$V_{GS}=V_G-I_D{R}_S$