FET biasing - 3 types

---

FET Biasing Configurations

Definition: Biasing is the procedure of applying specific DC voltages to a transistor to establish a fixed level of current ($I_{DQ}$) and voltage ($V_{GSQ}$, $V_{DSQ}$), known as the quiescent point or Q-point. Goal: To ensure the device operates in the active (saturation) region for linear amplification.

---

1. Fixed-Bias Configuration

Definition and Purpose

The simplest biasing arrangement that uses two separate DC voltage sources: one ($V_{DD}$) for the drain output and a specific battery ($V_{GG}$) to set the gate-to-source voltage.

Circuit Description

• $V_{GG}$: A DC voltage source connected to the Gate through resistor $R_G$. Its polarity ensures the Gate-Source junction is reverse-biased (negative potential at Gate for n-channel).
• $R_G$: Resistor connected to the Gate. Since $I_G\approx 0$ A, there is no voltage drop across $R_G$. It effectively applies $V_{GG}$ directly to the gate.
• $R_D$: Drain resistor used to define the output voltage swing.

Key Equations

1. Input Loop (Gate): $V_{GS}=-V_{GG}$ (Since $I_G=0$, $V_{R_G}=0$).
2. Device Equation (Shockley): $I_D=I_{DSS}{\left(1-\frac{V_{GS}}{V_P}\right)}^2$
3. Output Loop (Drain): $V_{DS}=V_{DD}-I_D{R}_D$

Working Principle

• Because the input impedance of a FET is infinite, no current flows into the Gate ($I_G=0$).
• Consequently, the voltage source $V_{GG}$ appears directly across the Gate-Source terminals.
• This fixes $V_{GS}$ at a constant value regardless of the current $I_D$. There is no feedback mechanism to stabilize the circuit against temperature changes or device parameter variations.

Step-by-Step Method for Numerical Problems

1. Calculate $V_{GSQ}$: Directly identify $V_{GSQ}=-V_{GG}$.
2. Calculate $I_{DQ}$: Substitute $V_{GSQ}$ into Shockley’s Equation.
3. Calculate $V_{DS}$: Use the output loop equation: $V_{DS}=V_{DD}-I_D{R}_D$.
4. Calculate $V_D,V_G,V_S$:
   • $V_S=0$ V (Source is grounded).
   • $V_D=V_{DS}$.
   • $V_G=V_{GS}$.

Advantages, Disadvantages, and Applications

• Advantages: Extremely simple circuit logic; mathematical solution is direct (no need for graphical methods).
• Disadvantages: Requires two separate power supplies; Poor stability (Q-point shifts significantly if FET parameters change).
• Applications: Rarely used in practical linear amplifiers; used in simple switching or logic circuits.

Exam Trend Analysis (PYQs)

• Frequency: Moderately frequent.
• Question Types:
  • Design: “Design a fixed bias circuit to obtain a specific load line/Q-point” .
  • Comparison: “Differences between self-bias and fixed bias” .
  • Numerical: “Determine $g_m,r_d,Z_i,Z_o$” for fixed bias .

---

2. Self-Bias Configuration

Definition and Purpose

A biasing method that eliminates the second battery ($V_{GG}$) by using a source resistor ($R_S$) to create a self-generated bias voltage. It is the most common discreet biasing method.

Circuit Description

• $R_S$: A resistor inserted at the Source terminal. Current $I_D$ flowing through $R_S$ creates a voltage drop $V_S$.
• Gate Connection: The Gate is connected directly to ground via $R_G$.

Key Equations

1. Input Loop (Bias Line Equation): $V_{GS}=-I_D{R}_S$ (This is a straight line passing through the origin).
2. Output Loop: $V_{DS}=V_{DD}-I_D(R_D+R_S)$
3. Voltages to Ground: $V_S=I_D{R}_S$ $V_G=0$ V

Working Principle (Stabilization)

• Establishment: Current $I_D$ flows through $R_S$, making the Source positive ($V_S>0$). Since Gate is at 0V, $V_{GS}=V_G-V_S=0-V_S=\text{negative}$. This provides the necessary reverse bias.
• Stabilization (Negative Feedback): If $I_D$ increases (due to temperature), the voltage drop across $R_S$ increases. This makes $V_{GS}$ more negative. A more negative $V_{GS}$ reduces $I_D$ (via Shockley’s equation), counteracting the initial increase.

Step-by-Step Method for Numerical Problems

Since the intersection of a line and a curve requires solving a quadratic equation, the Graphical Method is preferred.

1. Plot the Transfer Curve: Use $I_{DSS}$ and $V_P$ to plot $I_D=I_{DSS}(1-V_{GS}/V_P{)}^2$.
2. Plot the Bias Line: Plot $V_{GS}=-I_D{R}_S$.
   • Point 1: $(0,0)$.
   • Point 2: Choose a convenient $I_D$ (e.g., $I_{DSS}/2$) and calculate corresponding $V_{GS}$.
3. Find Q-Point: The intersection of the straight line and the curve is $(V_{GSQ},I_{DQ})$.
4. Solve Output: Use derived $I_{DQ}$ to find $V_{DS}$, $V_S$, and $V_D$.

Advantages, Disadvantages, and Applications

• Advantages: Single power supply; better stability than fixed-bias due to feedback action of $R_S$.
• Disadvantages: Gain is reduced unless $R_S$ is bypassed by a capacitor ($C_S$) in AC operation.
• Applications: General-purpose amplifiers.

Exam Trend Analysis (PYQs)

• Frequency: High Yield (Very Common).
• Question Types:
  • Calculation: “Determine $V_{GSQ},I_{DQ},V_{DS},V_D,V_G,V_S$” .
  • Derivation: “For JFET self-bias, prove that $V_D=V_{DD}-V_{RD}$” .
  • Comparison: Compare gain with bypassed vs. unbypassed $R_S$ .

---

3. Voltage-Divider Bias Configuration

Definition and Purpose

A configuration that uses a resistive divider ($R_1$ and $R_2$) at the gate to establish a fixed gate voltage ($V_G$), independent of the device. This provides the highest stability of the three methods.

Circuit Description

• $R_1$ and $R_2$: Form a voltage divider across $V_{DD}$ to provide a fixed positive voltage at the Gate.
• $R_S$: Source resistor. Ideally, $V_S$ tracks $V_G$ to maintain bias.

Key Equations

1. Gate Voltage ($V_G$): $V_G=\frac{R_2{V}_{DD}}{R_1+R_2}$
2. Input Loop (Bias Line Equation): $V_{GS}=V_G-I_D{R}_S$
3. Output Loop: $V_{DS}=V_{DD}-I_D(R_D+R_S)$

Working Principle

• Ideally, $I_G=0$, so the voltage at the gate is strictly set by the resistors $R_1$ and $R_2$.
• The source voltage $V_S$ is determined by $I_D{R}_S$.
• The actual bias $V_{GS}$ is the difference between the fixed gate voltage and the source voltage. This arrangement desensitizes the operating point from changes in the FET parameters ($V_P,I_{DSS}$).

Step-by-Step Method for Numerical Problems

1. Calculate $V_G$: Use the voltage divider formula.
2. Plot Transfer Curve: Plot Shockley’s equation.
3. Plot Bias Line: Plot $V_{GS}=V_G-I_D{R}_S$.
   • Point 1: If $I_D=0$, $V_{GS}=V_G$ (Intercept on X-axis).
   • Point 2: If $V_{GS}=0$, $I_D=V_G/R_S$ (Intercept on Y-axis).
4. Find Q-Point: The intersection is the solution.
5. Calculate Output: Use loop equations for $V_{DS}$.

Advantages, Disadvantages, and Applications

• Advantages: Excellent stability against device variations; Q-point is largely defined by external resistors.
• Disadvantages: More components required.
• Applications: High-quality linear amplifiers where Q-point stability is critical.

Exam Trend Analysis (PYQs)

• Frequency: High Yield (Commonly asked).
• Question Types:
  • Calculation: “Determine $I_{DQ},V_{GSQ},V_D,V_S$” .
  • Explanation: “Explain voltage divider biasing… discuss effect of $R_S$” .
  • Conditions: “What is the condition for approximate analysis?” .

---

Summary of Important Exam Points

• Graphical Solution: You must know how to plot the straight line (bias equation) on the transfer curve (Shockley’s equation) to find the Q-point. This is the standard method for solving Self-Bias and Voltage-Divider problems in exams.
• Stability: If asked which is best, the answer is Voltage-Divider Bias. If asked for the simplest, it is Fixed-Bias.
• Assumption: Always assume $I_G=0$ A for DC analysis