FET bias part 2 note

Related Concepts: FET mosfet biasing | FET biasing - 3 types | FET biasing concepts

FET Biasing (Part 2: Advanced Configurations & MOSFETs)

1. Common-Gate Configuration

(Source: 7.5,)

Concept & Circuit

In this configuration, the Gate is grounded, the input signal is typically applied to the Source, and the output is taken from the Drain. This is analogous to the Common-Base configuration in BJTs.

• Key Feature: High stability but low input impedance.

DC Analysis

1. Input Loop ($V_{GS}$ Calculation): Applying Kirchhoff’s Voltage Law (KVL) to the source loop: $-V_{GS}-I_S{R}_S+V_{SS}=0$ Since $I_S=I_D$: $V_{GS}=V_{SS}-I_D{R}_S$ (Note: This equation is linear. To find the Q-point, plot this line on the JFET transfer curve).

2. Output Loop: $V_{DS}=V_{DD}+V_{SS}-I_D(R_D+R_S)$ (Note: $V_{DD}$ is positive, $V_{SS}$ is usually a negative supply relative to ground, but treated as a magnitude in this KVL).

3. Terminal Voltages:

• $V_D=V_{DD}-I_D{R}_D$
• $V_S=-V_{SS}+I_D{R}_S$
• $V_G=0V$

PYQ Relevance (High)

• Numerical Problems: Questions asking to determine $I_D,V_S,V_{DS},V_G$ for common-gate circuits appeared in 2020 and 2021.
• Derivation: Be prepared to write the KVL loop for the input to derive the bias line equation.

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2. Special Case: $V_{GSQ}=0$ V

(Source: 7.6,)

Concept

This occurs when the Gate is connected directly to the Source.

• Condition: $V_{GS}=0V$.
• Current: By definition of the JFET parameters, when $V_{GS}=0$, the drain current is at its maximum saturation level. $I_{DQ}=I_{DSS}$
• Circuit Implication: No transfer curve plotting is required. You immediately know current is $I_{DSS}$ and can solve for output voltages using Ohm’s law.

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3. Depletion-Type MOSFET Biasing

(Source: 7.7,)

Working Principle

Depletion MOSFETs (D-MOSFETs) have a physical channel. They can operate in:

1. Depletion Mode: Negative $V_{GS}$ (like a JFET).
2. Enhancement Mode: Positive $V_{GS}$ (attracting more carriers).

Analysis Method

The DC analysis is identical to JFETs (Fixed, Self, and Voltage-Divider bias) because both use Shockley’s Equation: $I_D=I_{DSS}{\left(1-\frac{V_{GS}}{V_P}\right)}^2$

Key Difference: When plotting the transfer curve, you must extend the curve into the positive $V_{GS}$ region (for n-channel). $I_D$ can exceed $I_{DSS}$.

PYQ Relevance (Theory)

• Theory: “Distinguish between depletion and enhancement MOSFET” (2021, 2019).
• Diagrams: Sketching transfer characteristics showing operation in both positive and negative $V_{GS}$ regions.

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4. Enhancement-Type MOSFET Biasing

(Source: 7.8,)

Concept

E-MOSFETs have no physical channel. A channel is induced only when $V_{GS}$ exceeds the Threshold Voltage ($V_T$).

• Shockley’s equation does NOT apply.
• Current Equation: $I_D=k(V_{GS}-V_T{)}^2$ Where $k$ is a constant determined by specific coordinates ($I_{D(on)},V_{GS(on)}$) given in datasheets: $k=\frac{I_{D(on)}}{(V_{GS(on)}-V_T{)}^2}$

A. Feedback Biasing Arrangement

• Circuit: A resistor ($R_G$) is connected directly between the Drain and the Gate.
• Principle: Since $I_G=0$, there is no voltage drop across $R_G$. Therefore: $V_G=V_D⟹V_{GS}=V_{DS}$
• Analysis: This provides a feedback loop. If $I_D$ increases, $V_{DS}$ decreases (due to $R_D$), which decreases $V_{GS}$, reducing $I_D$. This stabilizes the Q-point.
• Bias Line Equation: $V_{GS}=V_{DD}-I_D{R}_D$ (Plot this line against the $I_D=k(V_{GS}-V_T{)}^2$ curve to find the Q-point).

B. Voltage-Divider Biasing

• Circuit: Standard divider ($R_1,R_2$) sets $V_G$.
• Equations: $V_G=\frac{R_2{V}_{DD}}{R_1+R_2}$ $V_{GS}=V_G-I_D{R}_S$ (Same graphical solution method as JFETs, but using the E-MOSFET transfer curve).

PYQ Relevance (Theory & Conceptual)

• Construction/Operation: Questions on “Construction and basic operation of n-channel enhancement MOSFET” (2022).
• Comparison: Differences between Depletion and Enhancement types (2016).

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5. p-Channel FETs

(Source: 7.13,)

Concept

• Structure: p-type channel, n-type gate.
• Reversals:
  • Voltages ($V_{DD},V_{GG}$) are negative.
  • Current ($I_D$) flows out of the source.
  • $V_{GS}$ is positive for JFETs (reverse bias).

Analysis Strategy

Treat it exactly like an n-channel device for calculation magnitudes, but reverse the signs of the final voltage answers and current directions.

• Graphing: The transfer curve is the mirror image of the n-channel curve (flipped across the $I_D$ axis).

PYQ Relevance

• Comparison: “Distinguish between p-channel and n-channel JFET” (2019, 2016).
• Sketching: “Sketch transfer characteristics” (2019).

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6. Combination Networks

(Source: 7.10,)

Concept

Circuits that combine JFETs with BJTs or other FETs.

• Example: A JFET driving a BJT, or a cascade arrangement.
• Analysis Strategy:
  1. Solve the FET stage first (usually independent due to high input impedance).
  2. Use the output of the FET stage (e.g., $V_D$) as the input voltage or bias for the BJT stage.
  3. Remember: Coupling capacitors are open circuits for DC.

PYQ Relevance (Numerical)

• Complex circuit diagrams in exams often involve combination networks.
• Strategy: Isolate the FET part, solve for $V_G$ or $V_D$, and pass that value to the next transistor.

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7. Design Problems

(Source: 7.11,)

Concept

Instead of finding the Q-point given the resistors, you are given the Q-point ($I_{DQ},V_{GSQ}$) and asked to find the resistor values ($R_D,R_S,R_1,R_2$).

Method

1. Find $R_S$: Use Ohm’s law on the source leg. $R_S=\frac{V_S}{I_D}$ (For self-bias, remember $V_S=-V_{GS}$ or determined by divider).
2. Find $R_D$: Use Ohm’s law on the drain leg. $R_D=\frac{V_{DD}-V_D}{I_D}$

PYQ Relevance (High)

• Design Questions: “Design a voltage-divider bias network…” (2020).
• Fixed Bias Design: “Design a fixed bias circuit…” (2018, 2016).
• Steps: These require manipulating the loop equations algebraically rather than using graphs.

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8. Universal JFET Bias Curve

(Source: 7.14,)

• Concept: A single normalized graph ($I_D/I_{DSS}$ vs $V_{GS}/|V_P|$) that can solve the DC bias for any JFET, eliminating the need to redraw the Shockley curve for every problem.
• Relevance: Useful for understanding the general behavior of bias points (m-scales), but in exams, specific graphical solutions (plotting the specific device curve) are usually preferred/required.

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9. Practical Applications

(Source: 7.15,)

A. Voltage-Controlled Resistor (VCR)

• Region: JFET in the ohmic region (small $V_{DS}$).
• Principle: The resistance $R_{DS}$ changes with $V_{GS}$.
• Use: Automatic gain control circuits.

B. MOSFET Relay Driver

• Concept: Because MOSFETs have extremely high input impedance, a very weak source (like a sensor or logic gate) can drive a high-current load (relay/motor) through the MOSFET without loading down the source.

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Summary of Key Equations for Exam

Device	$I_D$ Equation (Device)	Bias Equation (Circuit - Self Bias)	Bias Equation (Circuit - Voltage Divider)
JFET / Depletion MOS	$I_D=I_{DSS}(1-\frac{V_{GS}}{V_P}{)}^2$	$V_{GS}=-I_D{R}_S$	$V_{GS}=V_G-I_D{R}_S$
Enhancement MOS	$I_D=k(V_{GS}-V_T{)}^2$	N/A (Uses Feedback)	$V_{GS}=V_G-I_D{R}_S$
Common-Gate (JFET)	Shockley’s Equation	$V_{GS}=V_{SS}-I_D{R}_S$	N/A
Feedback Bias (E-MOS)	$I_D=k(V_{GS}-V_T{)}^2$	$V_{GS}=V_{DS}=V_{DD}-I_D{R}_D$	N/A