fet ac theoritical pyq

Here is your strictly PYQ-focused, exam-standard study note covering all theory questions asked regarding FET AC Analysis and Characteristics, specifically excluding the mathematical derivations and numericals.

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1. BJT vs. FET Amplifiers (Core Differences)

• Exact PYQs:
  • “Write down the differences between BJT and FET.” (Asked in: 2023, 2017, 2016)

The Differences:

• Device Type: A BJT is a bipolar device, meaning its conduction depends on two charge carriers (electrons and holes). A FET is a unipolar device, depending solely on either electron (n-channel) or hole (p-channel) conduction.
• Control Mechanism: The BJT is a current-controlled device (a small input base current controls the large output collector current). The FET is a voltage-controlled device (an input gate-to-source voltage controls the output drain current).
• Input Impedance: FETs have vastly higher input impedance (megohms to hundreds of megohms) compared to the relatively low input resistance of BJTs.
• Voltage Gain: Typical AC voltage gains for BJT amplifiers are significantly higher than those of FET amplifiers.
• Thermal Stability: FETs are much more temperature-stable than BJTs because their majority-carrier current decreases with rising temperature, completely avoiding the thermal runaway phenomenon that plagues BJTs.

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2. The Reason for High Input Impedance in FETs

• Exact PYQs:
  • “Briefly explain the reasons behind the higher input impedance of FET.” (Asked in: 2018)
  • “Distinguish between depletion type and enhancement type MOSFET, why is the input impedance of MOSFET so high? Explain in brief.” (Asked in: 2021, 2019)

The Justification:

• For JFETs: During standard operation, the gate-to-source PN junction of a JFET is always reverse-biased. Because a reverse-biased junction draws practically zero current (leakage current is in the nanoampere range), it inherently presents an extremely high input impedance to any AC signal.
• For MOSFETs: The input impedance of a MOSFET is even higher than that of a JFET ($10^{10}\Omega$ to $10^{14}\Omega$). This is because the metal gate is completely electrically isolated from the semiconductor channel by a thin dielectric layer of silicon dioxide ($Si{O}_2$). Because there is no direct electrical connection, virtually zero gate current can flow, resulting in an exceptionally high input resistance.

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3. Transconductance ($g_m$) & The Effect of Drain Current

• Exact PYQs:
  • “Derive the mathematical definition of transconductance. Explain the effect of drain current on transconductance factor of FET.” (Asked in: 2023, 2017)
  • “Define transconductance ($g_m$).” (Asked in: 2020)

Mathematical Definition: In FET AC analysis, transconductance ($g_m$) is the AC amplification factor. It is defined mathematically as the ratio of the change in output drain current ($\Delta I_D$) to the corresponding change in the input gate-to-source voltage ($\Delta V_{GS}$), with the drain-to-source voltage ($V_{DS}$) kept constant. Graphically, it is the slope of the transfer characteristic curve at the Q-point. Formula: $g_m=\frac{\Delta I_D}{\Delta V_{GS}}$.

Effect of Drain Current ($I_D$): The transconductance factor is directly dependent on the level of drain current. According to the relationship $g_m=g_{m0}\sqrt{\frac{I_D}{I_{DSS}}}$, as the drain current ($I_D$) increases, the transconductance ($g_m$) also increases non-linearly. The maximum value of transconductance ($g_{m0}$) is achieved when the drain current reaches its maximum saturation level ($I_{DSS}$) at $V_{GS}=0V$.

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4. Effect of Output Resistance ($r_d$) on AC Parameters

• Exact PYQs:
  • “…determine (iii) $Z_i$, (iv) $Z_o$, (v) $A_v$ with and without $r_d$. Also give comments on the effect of $r_d$ on $A_v$.” (Asked in: 2023, 2015)

When analyzing a FET amplifier, including the device’s internal output drain resistance ($r_d$) alters the circuit’s performance in specific ways:

• On Voltage Gain ($A_v$): Including $r_d$ places it in parallel with the external drain resistor ($R_D$). Because $A_v=-g_m(r_d||R_D)$, this parallel combination lowers the effective output resistance, which directly reduces the overall voltage gain. (Note: If $r_d\ge 10R_D$, the decrease is negligible and can be ignored).
• On Output Impedance ($Z_o$): Similarly, $r_d$ appears in parallel with $R_D$ when calculating output impedance ($Z_o=r_d||R_D$). Therefore, including $r_d$ decreases the output impedance.
• On Input Impedance ($Z_i$): Because the input gate circuit is isolated from the output drain circuit, changes in $r_d$ have no effect whatsoever on the input impedance ($Z_i$).

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5. Unbypassed vs. Bypassed Source Resistor ($R_S$)

• Exact PYQs:
  • “For a self-bias configuration of JFET amplifier, show that the voltage gain with unbypassed $R_S$ is less than the voltage gain with bypassed $R_S$.” (Asked in: 2015)

The Conceptual Proof:

• Bypassed $R_S$: If an AC bypass capacitor ($C_S$) is connected across $R_S$, it acts as an AC short circuit. This entirely removes $R_S$ from the AC equivalent model, preventing any signal voltage from dropping across it, which yields the maximum possible voltage gain for the configuration ($A_v=-g_m{R}_D$).
• Unbypassed $R_S$: Without the bypass capacitor, $R_S$ remains in the AC circuit and generates a feedback voltage ($V_S=I_d{R}_S$). This creates negative AC feedback (degeneration) that opposes the input signal, meaning less effective voltage reaches the gate-to-source junction to control the FET. As a result, the voltage gain drops significantly ($A_v=\frac{-g_m{R}_D}{1+g_m{R}_S}$). Therefore, the unbypassed gain is always less than the bypassed gain.

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6. Fixed-Bias vs. Self-Bias Configurations

• Exact PYQs:

  • “Write down the differences between self-bias and fixed bias configuration of FET.” (Asked in: 2016)

• Fixed-Bias: This configuration requires two separate DC voltage supplies. A dedicated negative battery ($V_{GG}$) is connected directly to the gate to establish a fixed, unchanging $V_{GS}$ operating point.

• Self-Bias: This configuration is more practical because it eliminates the need for a second DC supply, relying solely on $V_{DD}$. Instead of a fixed battery, a source resistor ($R_S$) is introduced. The normal drain current flowing through $R_S$ creates a voltage drop that automatically establishes the required negative gate-to-source bias voltage ($V_{GS}=-I_D{R}_S$).