direct coupling

Related Concepts: rc coupling | Common emitter | complementary power amplifier

Based on Laboratory Exercise 18: Direct Coupling from your manual, here is the revision note.

(Note: The manual skips from Exercise 16 to 18; Exercise 17 is not present in the provided pages.)

1) Experiment Snapshot

Experiment Title: Direct Coupling (Two-Stage Amplifier)

Objective(s):

Identify a two-stage direct-coupled amplifier (NPN to PNP) and measure DC voltages.
Measure AC voltage gains with and without emitter bypassing.
Determine the frequency response of the direct-coupled amplifier.

Core Principle / Theory:

Direct Coupling: The output of the first stage is connected directly to the input of the next without capacitors or transformers.
Frequency Response: Excellent low-frequency response (down to DC) because there are no coupling capacitors to block low signals ( $X_{C} = \infty$ at DC).
Complementary Stages: Uses an NPN transistor (Q1) driving a PNP transistor (Q2) to simplify biasing and level shifting.
Stability: Direct coupling is sensitive to temperature changes (drift), requiring stabilizing circuits.

Key Formula(s):

Voltage Gain: $A_{V} = \frac{e _{o u t}}{e _{in}}$
Total Gain: $A_{t o t a l} = A_{V 1} \times A_{V 2}$
Emitter Current: $I_{E} = \frac{V _{E}}{R _{E}}$

2) Apparatus Setup

Connection / Block Diagram:

Stage 1 (Q1 - NPN): Input at Base. Collector connected directly to the Base of Stage 2.
Stage 2 (Q2 - PNP): Base connected to Q1 Collector. Output taken from Collector of Q2.
Feedback/Bias: $R 1$ (Potentiometer) sets the bias for the base of Q1.
Supply: $V_{CC} = 24 V$ .
Components: NPN (2N2219A), PNP (2N2905A), Potentiometer ( $500 k Ω$ ), Resistors ( $150 k, 10 k, 1 k, 470, 4.7 k, 22 k Ω$ ).

Precautions:

Bias Adjustment: $R 1$ must be adjusted carefully to set the proper operating point ( $V_{C 1}$ ) before taking AC readings, or the signal will clip.
Shorts: Since stages are directly connected, a short in one stage drastically affects the DC levels of the other.

3) Procedure

Part A: DC Operation

Connect the circuit (Fig 18-2). Note that Q2 is PNP (upside down symbol).
Set Supply $V_{CC}$ to 24V DC. Input signal $e_{i} = 0$ .
Adjust Potentiometer $R 1$ until the collector voltage of Q1 ( $V_{C 1}$ ) reads 22.5V DC.
Measure and record DC voltages:
- Q1: Base ( $V_{B 1}$ ), Emitter ( $V_{E 1}$ ).
- Q2: Base ( $V_{B 2}$ ), Emitter ( $V_{E 2}$ ), Collector ( $V_{C 2}$ ).

Part B: AC Gain Measurement 5. Set AF Generator to 1kHz Sine Wave. 6. Adjust input ( $e_{i}$ ) to 100mV pk-pk at the Base of Q1. 7. Measure output of Stage 1 ( $e_{c 1}$ ) and Output of Stage 2 ( $e_{o}$ ). 8. Calculate individual and total gains ( $A_{V 1}, A_{V 2}, A_{T o t a l}$ ). 9. Load Test: Connect external load $R 9$ ( $22 k Ω$ ). Measure $e_{o}$ . 10. Bypass Test: Connect capacitor $C 3$ across Q2’s emitter resistor $R 6$ . Measure $e_{o}$ (distortion check).

Part C: Frequency Response 11. Remove bypass capacitor C3. 12. Maintain input at 100mV pk-pk. 13. Sweep frequency from 20Hz to 100kHz (Table 18-1). 14. Measure output voltage ( $e_{o}$ ) at each step.

4) Data Taken / Measurements

Table 1: DC Conditions

Parameter	Measured Value	Unit	Target/Note
$V_{C 1}$	________ (Set to 22.5)	Vdc	Adjust R1 to get this
$V_{B 1}$	________	Vdc	~0.75V
$V_{E 1}$	________	Vdc	~0.15V
$V_{B 2}$	________	Vdc	Should equal $V_{C 1}$
$V_{E 2}$	________	Vdc	~ $V_{B 2} + 0.6 V$

Table 2: AC Gain (1kHz)

Input/Output	Value	Unit	Gain Calc
Input ( $e_{i}$ )	0.1	$V_{pp}$	-
Stage 1 Out ( $e_{c 1}$ )	________	$V_{pp}$	$A_{V 1} = e_{c 1} / e_{i}$
Stage 2 Out ( $e_{o}$ )	________	$V_{pp}$	$A_{V 2} = e_{o} / e_{c 1}$

Table 3: Frequency Response

Frequency	Output ( $V_{pp}$ )
20 Hz	_______
…	…
100 kHz	_______

5) Calculations

First Stage Gain: $A_{V 1} = \frac{e _{c 1}}{e _{i}} \approx \frac{0.8 V}{0.1 V} = 8$
Second Stage Gain: $A_{V 2} = \frac{e _{o}}{e _{c 1}}$
Total Gain: $A_{V} = A_{V 1} \times A_{V 2}$ (Manual expects Total Gain between 70 and 80).

6) Results & Outcome

DC Bias:
- Q1 is forward biased ( $V_{B} > V_{E}$ ).
- Q2 (PNP) is forward biased ( $V_{E} > V_{B}$ by approx 0.6V).
- $V_{B 2}$ is exactly the same as $V_{C 1}$ due to the direct wire connection.
Gain: The amplifier provides significant voltage gain (Manual suggests ~75).
Frequency Response: The response is flat across the measured audio range (20Hz to 20kHz). Unlike RC coupling, there is no drop-off at low frequencies (20Hz).

7) Why This Outcome Happens (Reasoning)

Flat Low-Frequency Response: Since there are no coupling capacitors between stages (Direct Coupling), there is no capacitive reactance ( $X_{C} = \frac{1}{2 π f C}$ ) to increase at low frequencies and block the signal. The gain remains constant down to DC.
Complementary Design: Using NPN followed by PNP allows the high collector voltage of Q1 to directly bias the base of Q2 without complex resistive dividers.
Drift: If the output voltage drifts during the experiment, it is likely due to temperature changes affecting $V_{BE}$ and leakage currents, which are amplified by subsequent direct-coupled stages.

8) Viva / Lab Test Quick Prep

Q1: What is the main advantage of Direct Coupling? A: It provides excellent low-frequency response (can amplify DC signals) and uses fewer components (no capacitors).

Q2: What is the main disadvantage? A: DC stability/Drift. Any change in DC bias (due to temperature/noise) in the first stage is amplified by the second stage.

Q3: Why use an NPN and then a PNP transistor? A: It simplifies the design (Complementary symmetry). The collector of the NPN sits at a high positive voltage, which is convenient for biasing the base of a PNP transistor.

Q4: How does the frequency response compare to RC coupling? A: Direct coupling is flat down to 0Hz (DC), whereas RC coupling drops off at low frequencies due to capacitor reactance.

Q5: What happens if you bypass the emitter resistor of the second stage? A: The AC gain increases significantly, but distortion may occur if the signal becomes too large.

Q6: Why must $V_{C 1}$ be adjusted to a specific value (22.5V)? A: To ensure Q2 is properly biased. Since Q1 collector drives Q2 base, $V_{C 1}$ determines the Q-point of the second stage.

Common Mistakes:

Biasing: Failing to adjust $R 1$ initially leads to a saturated or cutoff output (distorted or zero signal).
Transistor ID: Confusing the NPN and PNP transistors (check part numbers 2N2219A vs 2N2905A).

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