Bjt biasing types

Related Concepts: Bjt biasing stabilization | Bjt biasing book references

Here is a detailed, self-explanatory study guide on the three primary types of BJT DC biasing. This guide breaks down the core concepts, necessary equations, textbook examples, and how these topics are specifically tested in your ECE 1209 exams based on past year questions (PYQs).

The primary goal of DC biasing is to establish a stable operating point (Q-point), defined by the collector current ($I_{CQ}$) and collector-to-emitter voltage ($V_{CEQ}$), ensuring the transistor operates in the active region for amplification.

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1. Fixed-Bias Configuration

This is the simplest BJT biasing arrangement, but it is highly unstable because its operating point is extremely sensitive to changes in the transistor’s beta ($\beta$) value.

• Circuit Reference: Refer to Fig. 4.2 in Boylestad. The circuit consists of a single DC supply ($V_{CC}$) connected to both a base resistor ($R_B$) and a collector resistor ($R_C$).
• Concept & Equations:
  • Base-Emitter Loop: By applying Kirchhoff’s Voltage Law (KVL) to the input loop, the base current is determined by the supply voltage minus the base-emitter drop ($V_{BE}\approx 0.7\text{ V}$), divided by the base resistor: $I_B=\frac{V_{CC}-V_{BE}}{R_B}$.
  • Collector-Emitter Loop: The collector current is $I_C=\beta I_B$. Applying KVL to the output loop gives the voltage across the transistor: $V_{CE}=V_{CC}-I_C{R}_C$.
• Example (from Example 4.1): Given $V_{CC}=12\text{ V}$, $R_B=240\text{ k}\Omega$, $R_C=2.2\text{ k}\Omega$, and $\beta =50$:
  • $I_B=(12\text{ V}-0.7\text{ V})/240\text{ k}\Omega =47.08\mu \text{A}$.
  • $I_C=50\times 47.08\mu \text{A}=2.35\text{ mA}$.
  • $V_{CE}=12\text{ V}-(2.35\text{ mA})(2.2\text{ k}\Omega )=6.83\text{ V}$.

📝 PYQs & Exam Trends for Fixed-Bias:

• 2023, Q1(a): “Define load line and explain it’s significance. Explain the effect of changing the circuit elements of a fixed bias common emitter circuit on the transistor operating point.”
• 2018, Q1(a): “What is the necessity of transistor biasing? Design a fixed bias circuit in order to obtain the following load line and Q-point.” (A load line graph was provided).
• Question Trend: The professor rarely asks you to simply calculate $I_C$ and $V_{CE}$ for this circuit. Instead, questions focus on Load Line Analysis and Design. You must know how to draw a DC load line (where $I_{C_{sat}}=V_{CC}/R_C$ and $V_{C{E}_{cutoff}}=V_{CC}$) and explain how altering $R_B$, $R_C$, or $V_{CC}$ shifts the Q-point.

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2. Emitter-Bias Configuration

This configuration improves upon the fixed-bias circuit by adding a resistor ($R_E$) to the emitter leg. This resistor provides a feedback mechanism that stabilizes the Q-point against changes in temperature and $\beta$.

• Circuit Reference: Refer to Fig. 4.17 in Boylestad.
• Concept & Equations:
  • Base-Emitter Loop: Because the emitter current is $I_E=(\beta +1)I_B$, the emitter resistor $R_E$ is “seen” at the base as a much larger reflected resistance equal to $(\beta +1)R_E$. The base current equation becomes: $I_B=\frac{V_{CC}-V_{BE}}{R_B+(\beta +1)R_E}$.
  • Collector-Emitter Loop: Output KVL includes the drop across $R_E$: $V_{CE}=V_{CC}-I_C(R_C+R_E)$.
• Example (from Example 4.4): Given $V_{CC}=20\text{ V}$, $R_B=430\text{ k}\Omega$, $R_C=2\text{ k}\Omega$, $R_E=1\text{ k}\Omega$, and $\beta =50$:
  • $I_B=(20\text{ V}-0.7\text{ V})/[430\text{ k}\Omega +(51)(1\text{ k}\Omega )]=40.1\mu \text{A}$.
  • $I_C=50\times 40.1\mu \text{A}=2.01\text{ mA}$.
  • $V_{CE}=20\text{ V}-(2.01\text{ mA})(2\text{ k}\Omega +1\text{ k}\Omega )=13.97\text{ V}$.

📝 PYQs & Exam Trends for Emitter-Bias:

• 2023, Q2(c): “Determine $R_C,R_E$ and $R_B$ for the emitter bias configuration… given $I_{CQ}=1/2I_{Csat}$, $I_{Csat}=8\text{ mA}$, $V_C=18\text{ V}$, and $\beta =110$.”
• 2022, Q3(a): “What is the significance of emitter resistor in emitter bias configuration? What are the effects of a bypass capacitor on the voltage gain of an amplifier?”
• Question Trend: Expect Reverse Design Problems where you are given the Q-point and must find the resistor values. Conceptually, you must be able to explain exactly how $R_E$ improves stability (i.e., if $I_C$ increases, $V_E$ increases, which reduces $V_{BE}$ and subsequently lowers $I_B$ to counteract the rise in $I_C$).

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3. Voltage-Divider Bias Configuration

This is the most widely used and tested configuration. Its popularity stems from the fact that, if designed correctly, its operating point ($I_{CQ},V_{CEQ}$) is almost completely independent of the transistor’s $\beta$ value.

• Circuit Reference: Refer to Fig. 4.28 in Boylestad. It uses two resistors ($R_1$ and $R_2$) at the base to form a voltage divider.
• Concepts & Equations: There are two ways to solve this—Exact and Approximate.
  • The Approximate Method: This is valid ONLY if the condition $\beta R_E\ge 10R_2$ is satisfied. It assumes the base current is so small it doesn’t affect the voltage divider.
    1. Base Voltage: $V_B\approx \frac{R_2{V}_{CC}}{R_1+R_2}$.
    2. Emitter Voltage: $V_E=V_B-V_{BE}$.
    3. Collector Current: $I_C\approx I_E=\frac{V_E}{R_E}$.
    4. Output Voltage: $V_{CE}=V_{CC}-I_C(R_C+R_E)$.
  • The Exact Method (Thévenin): Used if the approximation condition fails.
    1. $R_{Th}=R_1||R_2$ and $E_{Th}=\frac{R_2{V}_{CC}}{R_1+R_2}$.
    2. $I_B=\frac{E_{Th}-V_{BE}}{R_{Th}+(\beta +1)R_E}$.
• Example (from Example 4.8): Given $V_{CC}=22\text{ V}$, $R_1=39\text{ k}\Omega$, $R_2=3.9\text{ k}\Omega$, $R_C=10\text{ k}\Omega$, $R_E=1.5\text{ k}\Omega$, $\beta =100$:
  • Check condition: $100(1.5\text{ k}\Omega )=150\text{ k}\Omega \ge 10(3.9\text{ k}\Omega )=39\text{ k}\Omega$. (Satisfied).
  • $V_B=(3.9\text{ k}\Omega \times 22\text{ V})/(39\text{ k}\Omega +3.9\text{ k}\Omega )=2\text{ V}$.
  • $V_E=2\text{ V}-0.7\text{ V}=1.3\text{ V}$.
  • $I_{CQ}\approx I_E=1.3\text{ V}/1.5\text{ k}\Omega =0.867\text{ mA}$.
  • $V_{CEQ}=22\text{ V}-(0.867\text{ mA})(10\text{ k}\Omega +1.5\text{ k}\Omega )=12.03\text{ V}$.

📝 PYQs & Exam Trends for Voltage-Divider Bias:

• 2019, Q1(c): “Determine the levels $R_C,R_E,R_1$ and $R_2$ for the network in Fig. 1(c) with the operating point of $I_{CQ}=10$ mA and $V_{CEQ}=8$ V.”
• 2018, Q1(d): “What is the condition for approximate analysis of voltage divider bias configuration? Determine the values of $I_{CQ}$ and $V_{CEQ}$ of the following network using approximate analysis.”
• 2015, Q1(d): “Determine the values of $I_{CQ}$ and $V_{CEQ}$ for the voltage divider configuration of Fig. 1(d).”
• 2015, Q1(c): “Write the mathematical expressions of stability factors and hence show that voltage divider bias configuration is most stable.”
• Question Trend: This is the heavily tested configuration. You must memorize the condition $\beta R_E\ge 10R_2$. You will either be asked to solve for $I_{CQ}$ and $V_{CEQ}$ using the approximate method, or you will be given a target Q-point and asked to design the circuit (find $R_1,R_2,R_C,R_E$). Furthermore, proving mathematically via stability factor formulas $S(I_{CO})$ that this circuit is the most stable is a recurring theoretical question.

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While these don’t appear as standalone DC numericals as often as the main three, they are critical puzzle pieces for the high-weightage multistage amplifier and theory questions in your ECE 1209 exams.

1. Emitter-Follower (Common-Collector) Configuration

The Emitter-Follower configuration takes the output signal from the emitter terminal rather than the collector. It is primarily used for impedance matching because it has a high input impedance and a low output impedance.

• Circuit Reference: Refer to Fig. 4.46 in Boylestad. The collector is usually tied directly to ground (or directly to $V_{CC}$ with no resistor), and the output is measured across the emitter resistor $R_E$.
• Concept & Equations:
  • Input Loop: Applying KVL to the base-emitter loop yields $V_{EE}-I_B{R}_B-V_{BE}-I_E{R}_E=0$.
  • Because $I_E=(\beta +1)I_B$, the emitter resistor is reflected back to the base by a factor of $(\beta +1)$. Solving for base current gives: $I_B=\frac{V_{EE}-V_{BE}}{R_B+(\beta +1)R_E}$
  • Output Loop: Applying KVL to the collector-emitter loop gives: $V_{CE}=V_{EE}-I_E{R}_E$
• Example (from Example 4.16): Given $V_{EE}=20\text{ V}$, $R_B=240\text{ k}\Omega$, $R_E=2\text{ k}\Omega$, and $\beta =90$.
  • $I_B=(20\text{ V}-0.7\text{ V})/[240\text{ k}\Omega +(91)(2\text{ k}\Omega )]=45.73\mu \text{A}$.
  • $I_E=(\beta +1)I_B=(91)(45.73\mu \text{A})=4.16\text{ mA}$.
  • $V_{CE}=20\text{ V}-(91)(45.73\mu \text{A})(2\text{ k}\Omega )=11.68\text{ V}$.

📝 PYQs & Exam Trends for Emitter-Follower (CC):

• 2023 Q4(b), 2021 Q3(c), 2018 Q3(c), 2015 Q3(d): “Determine the input impedance and overall gain of the two-stage amplifier (CE-CC) using simplified model.” (A circuit diagram is provided with $Q_1$ as CE and $Q_2$ as CC).
• 2015 Q2(b): “Write the merits of emitter follower configuration. Using $r_e$ modeling concept, derive the expression for input impedance ($Z_i$) and output impedance ($Z_o$) for emitter follower configuration.”
• Question Trend: You will rarely be asked to solve a simple DC bias question for this. Instead, you must master its AC analysis. Understand that its voltage gain is always slightly less than 1 ($A_v\approx 1$), and be heavily prepared to solve the 14-to-16 mark CE-CC cascaded amplifier problems using h-parameters.

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2. Common-Base (CB) Configuration

The common-base configuration is unique because the input signal is applied to the emitter, the output is taken from the collector, and the base is grounded (common to both).

• Circuit Reference: Refer to Fig. 4.49 in Boylestad. It typically uses two power supplies ($V_{EE}$ and $V_{CC}$).
• Concept & Equations: Because the base is grounded, the input loop includes the emitter, making it very easy to find the emitter current first.
  • Input Loop: Applying KVL to the emitter-base loop: $-V_{EE}+I_E{R}_E+V_{BE}=0$. $I_E=\frac{V_{EE}-V_{BE}}{R_E}$
  • Output Loop: Because $I_C\approx I_E$, you can find the output voltages. Applying KVL to the entire outside perimeter gives: $V_{CE}=V_{EE}+V_{CC}-I_E(R_C+R_E)$ $V_{CB}=V_{CC}-I_C{R}_C$
• Example (from Example 4.17): Given $V_{EE}=4\text{ V}$, $R_E=1.2\text{ k}\Omega$, $V_{CC}=10\text{ V}$, $R_C=2.4\text{ k}\Omega$, and $\beta =60$.
  • $I_E=(4\text{ V}-0.7\text{ V})/1.2\text{ k}\Omega =2.75\text{ mA}$.
  • $I_B=I_E/(\beta +1)=2.75\text{ mA}/61=45.08\mu \text{A}$.
  • $V_{CE}=4\text{ V}+10\text{ V}-(2.75\text{ mA})(2.4\text{ k}\Omega +1.2\text{ k}\Omega )=4.1\text{ V}$.

📝 PYQs & Exam Trends for Common-Base:

• 2021 Q3(a) & 2016 Q3(a): “What are the advantages of hybrid model? Draw the exact and appropriate hybrid models of three common configurations.”
• Question Trend: This configuration is almost entirely tested via AC modeling theory. You must be able to accurately draw the common-base $r_e$ and Hybrid equivalent models. Standalone numericals for CB are very rare.

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3. Collector Feedback Configuration

This configuration improves DC stability by connecting a feedback resistor ($R_F$) directly from the collector to the base. If the temperature increases and collector current ($I_C$) tries to rise, the voltage drop across $R_C$ increases, which leaves less voltage for the base, automatically dropping $I_B$ to compensate.

• Circuit Reference: Refer to Fig. 4.38 in Boylestad.
• Concept & Equations:
  • Input Loop: The current flowing through $R_C$ is actually $I_C^{\prime }=I_C+I_B$. Because $I_B$ is very small, we approximate $I_C^{\prime }\approx I_C=\beta I_B$. Applying KVL to the base-emitter loop reflects both $R_C$ and $R_E$ back to the base by a factor of $\beta$: $I_B=\frac{V_{CC}-V_{BE}}{R_F+\beta (R_C+R_E)}$
  • Output Loop: Applying KVL to the collector-emitter loop yields the exact same equation as the emitter-bias and voltage-divider configurations: $V_{CE}=V_{CC}-I_C(R_C+R_E)$
• Example (from Example 4.12): Given $V_{CC}=10\text{ V}$, $R_C=4.7\text{ k}\Omega$, $R_F=250\text{ k}\Omega$, $R_E=1.2\text{ k}\Omega$, and $\beta =90$.
  • $I_B=(10\text{ V}-0.7\text{ V})/[250\text{ k}\Omega +90(4.7\text{ k}\Omega +1.2\text{ k}\Omega )]=11.91\mu \text{A}$.
  • $I_{CQ}=90\times 11.91\mu \text{A}=1.07\text{ mA}$.
  • $V_{CEQ}=10\text{ V}-(1.07\text{ mA})(4.7\text{ k}\Omega +1.2\text{ k}\Omega )=3.69\text{ V}$.

📝 PYQs & Exam Trends for Collector Feedback:

• 2017 Q1(d): “Determine the quiescent levels of $I_{CQ}$ and $V_{CEQ}$ for the following network shown in figure 1(d).” (A collector feedback circuit was provided).
• Question Trend: This is tested very infrequently (only once in recent years as a straightforward DC calculation). If it does appear, it is an easy 10 marks if you remember the $I_B$ formula. Simply remember that the feedback resistor $R_F$ takes the place of $R_B$, and $\beta$ multiplies both $R_C$ and $R_E$ in the denominator.