Bjt ac analysis book reference

Related Concepts: 02 AC Equivalent Circuit | AC load line

Here is the highly detailed, expanded study guide for Chapter 5: BJT AC Analysis. This version includes the critical mathematical formulas, derivation logic, circuit equivalents, and specific parameter definitions you must know for the ECE 1209 exam.

5.1 & 5.2 Introduction to Small-Signal Analysis

• The Core Principle: BJT AC analysis relies on the superposition theorem. You must first analyze the DC circuit to find the Q-point (specifically the DC emitter current, $I_E$), and then perform a completely separate AC analysis.
• The AC Golden Rules: To draw an AC equivalent circuit, you must:
  1. Set all DC voltage sources to zero (short circuit them to ground).
  2. Replace all capacitors (coupling and bypass) with short circuits.
• Exam Detail: The difference between large and small signal is linearity. Small AC signals operate on a tiny, linear segment of the transistor’s characteristic curve, allowing us to replace the physical transistor with a linear mathematical model.

5.3 & 5.4 The $r_e$ Transistor Model

• The Concept: This model replaces the transistor with a current-controlled current source and a dynamic internal resistance. The $r_e$ model has the advantage that its parameters are defined by the actual operating conditions of the circuit.
• The Key Formula: The dynamic emitter resistance is determined entirely by the DC analysis: $r_e=26\text{ mV}/I_E$.
• Common Emitter (CE) Equivalent: You must memorize this drawing. The input (base to emitter) is modeled as a resistor equal to $\beta r_e$. The output (collector to emitter) is modeled as a dependent current source flowing downward, defined as $\beta I_b$.

5.5 Common-Emitter (CE) Fixed-Bias Configuration

• Circuit Behavior: Known for high voltage gain, but introduces a 180° phase reversal between the input and output signals. This phase reversal occurs because an increase in base voltage reduces the collector voltage.
• Formulas to Master:
  • Input Impedance ($Z_i$): Looking into the base, the source sees the base resistor $R_B$ in parallel with the transistor’s input resistance: $Z_i=R_B||\beta r_e$.
  • Output Impedance ($Z_o$): $Z_o\approx R_C$ (assuming the internal device resistance $r_o$ is $\ge 10R_C$).
  • Voltage Gain ($A_v$): $A_v=-R_C/r_e$. The negative sign mathematically represents the 180° phase shift.

5.6 Voltage-Divider Bias Configuration

• Circuit Behavior: The AC equivalent circuit is virtually identical to the fixed-bias configuration. The only difference is that the two biasing resistors ($R_1$ and $R_2$) are now both connected to ground in the AC domain, placing them in parallel.
• Formulas to Master:
  • Let $R^{\prime }=R_1||R_2$.
  • $Z_i=R^{\prime }||\beta r_e$.
  • $Z_o\approx R_C$.
  • $A_v=-R_C/r_e$.

5.7 CE Emitter-Bias Configuration (The Most Tested)

This section is heavily tested because it involves the critical effect of the emitter bypass capacitor ($C_E$).

• Condition 1: Unbypassed ($C_E$ is removed or absent)
  • Without the bypass capacitor, the emitter resistance $R_E$ reduces the AC voltage gain.
  • The impedance looking into the base becomes $Z_b\approx \beta (r_e+R_E)$.
  • $Z_i=R_B||Z_b$.
  • Voltage Gain: $A_v=\frac{-R_C}{r_e+R_E}\approx \frac{-R_C}{R_E}$. Note that the gain is now defined by a resistor ratio and is completely independent of $\beta$, making it very stable but very low.
• Condition 2: Bypassed ($C_E$ is connected across $R_E$)
  • In the AC domain, the large capacitor acts as a short circuit, creating a zero-resistance path that completely bypasses $R_E$.
  • The circuit mathematically reverts exactly to the Fixed-Bias equations.
  • Voltage Gain: $A_v=-R_C/r_e$. Because $r_e$ is tiny compared to $R_E$, the gain skyrockets. You will be asked to mathematically prove this gain difference in the exam.

5.8 Emitter-Follower (Common Collector) Configuration

• Circuit Behavior: The output is taken from the emitter terminal instead of the collector. There is no phase shift between input and output.
• Why it is used: It is used primarily for impedance matching because it boasts a very high input impedance and a very low output impedance.
• Formulas to Master:
  • $Z_i=R_B||Z_b$, where $Z_b\approx \beta (r_e+R_E)$.
  • $Z_o=R_E||r_e\approx r_e$. (Since $r_e$ is tiny, output impedance is tiny).
  • Voltage Gain: $A_v=\frac{R_E}{r_e+R_E}\approx 1$. The voltage gain is always slightly less than 1.

5.12 & 5.15 Effect of Source ($R_s$) and Load ($R_L$) Resistors

• The Concept: The standard derivations ($A_{vNL}$) assume an ideal scenario. In reality, attaching a load resistor $R_L$ drastically drops the gain.
• Formulas to Master:
  • Loaded Voltage Gain ($A_{vL}$): The load resistor $R_L$ acts in parallel with the collector resistor $R_C$. Therefore, the new gain is $A_{vL}=\frac{-(R_C||R_L)}{r_e}$.
  • Overall System Gain ($A_{vs}$): The source resistance $R_s$ forms a voltage divider with the amplifier’s input impedance $Z_i$. The overall gain from the source is $A_{vs}=A_{vL}\times \frac{Z_i}{Z_i+R_s}$.
• Exam Detail: Memorize the rule: The greatest gain of an amplifier is the no-load gain.

5.16 Cascaded Systems

• The Concept: When connecting multiple amplifier stages, the total overall gain is the product of the individual stage gains: $A_{vT}=A_{v1}\times A_{v2}$.
• The Catch: You cannot use the “no-load” gain for Stage 1. The input impedance of Stage 2 ($Z_{i2}$) acts as the physical load resistor ($R_L$) for Stage 1.
• Exam Strategy: For the 14-mark CE-CC multistage exam question:
  1. Calculate $Z_{i2}$ of the Common Collector stage.
  2. Use $Z_{i2}$ as the $R_L$ parameter when calculating the gain of the Common Emitter stage.

5.17 Darlington Connection

• Circuit Behavior: Two BJTs connected such that the emitter of the first drives the base of the second. They act as a single unit.
• Key Characteristics:
  • Current gain is multiplied: ${\beta }_D={\beta }_1\times {\beta }_2$.
  • Extremely high input impedance: $Z_i={\beta }_1{\beta }_2{R}_E$.
• Exam Strategy: Practice drawing the circuit diagram and deriving the ${\beta }_D$ relationship, as this is explicitly highlighted in your syllabus.

5.19 to 5.21 The Hybrid Equivalent Model

• The Concept: While the $r_e$ model uses dynamic physical conditions, the hybrid equivalent circuit uses parameters defined in general terms on manufacturer specification sheets.
• The Four $h$-parameters:
  • $h_{ie}$ (Input impedance): Equivalent to $\beta r_e$.
  • $h_{fe}$ (Forward current gain): Equivalent to $\beta$.
  • $h_{re}$ (Reverse voltage transfer ratio): Models the feedback effect from output to input. Usually very small.
  • $h_{oe}$ (Output admittance): Equivalent to $1/r_o$.
• Derivations (The Exact Model): While the approximate model drops $h_{re}$ and $h_{oe}$, the PYQs require you to derive the exact equations.
  • Input Impedance: $Z_i=h_{ie}-\frac{h_{fe}{h}_{re}{R}_L}{1+h_{oe}{R}_L}$.
  • Voltage Gain: $A_v=\frac{-h_{fe}{R}_L}{h_{ie}+(h_{ie}{h}_{oe}-h_{fe}{h}_{re})R_L}$.
• Exam Strategy: You must be able to draw the precise blocks of the hybrid model: an input resistor ($h_{ie}$) in series with a dependent voltage source ($h_{re}{V}_o$), and an output dependent current source ($h_{fe}{I}_b$) in parallel with a resistor ($1/h_{oe}$). Be able to sketch this exact box for CE, CB, and CC configurations.