AC load line

Related Concepts: AC load line 1

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What is the AC Load Line (and Why Is It Useful)?

• AC load line shows how much the collector current ($i_C$) and collector-emitter voltage ($v_{CE}$) of a BJT amplifier can swing due to an AC signal, for a given bias.
• It is different from the DC load line (which uses only resistors in the DC analysis and sets the Q-point); the AC load line uses the parallel AC resistances (typically, $R_C$ // $R_L$), so it’s steeper and defines your max possible signal swing before distortion.

Why does this matter?

• The AC load line shows the true limits of your signal operation region: clipping/distortion occurs if the waveform tries to go past these calculated endpoints.
• Good amplifier design puts the DC Q-point in the middle of the AC load line, maximizing undistorted output.

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These equations are the mathematical foundation for drawing the AC Load Line on a transistor’s characteristic graph. They define the exact endpoints (the X and Y intercepts) of that line.

To understand where they come from, we have to look at how a transistor behaves when an AC signal is applied on top of the DC bias.

Here is the step-by-step breakdown of what these equations mean and how they are derived.

1. The Foundation: AC vs. DC Variables

When an AC signal is applied to an amplifier, the total instantaneous collector current ($i_C$) and voltage ($v_{CE}$) fluctuate around the fixed DC Q-point ($I_{CQ}$ and $V_{CEQ}$). Mathematically, this is written as:

• Total Current: $i_C=I_{CQ}+i_c$ (where $i_c$ is the AC fluctuation).
• Total Voltage: $v_{CE}=V_{CEQ}+v_{ce}$ (where $v_{ce}$ is the AC fluctuation).

In the AC equivalent circuit, all DC voltage sources are shorted to ground. Therefore, the AC collector voltage is simply the AC current multiplied by the equivalent AC resistance, but with a negative sign because the current direction causes a voltage drop:

• $v_{ce}=-i_c\cdot r_c$

2. Defining $r_c$ (AC Resistance)

In the specific circuit on your slide, $r_c$ represents the total AC resistance connected to the collector. Because coupling capacitors act as short circuits in AC analysis, the load resistor (let’s call it $R_1$) is placed in parallel with the collector resistor ($R_C$). Therefore, $r_c=R_C//R_1$.

3. Deriving $I_{C(sat)}$ (The Y-axis Intercept / Saturation Point)

The equation $I_{C(sat)}=I_{CQ}+(V_{CEQ}/r_c)$ determines the absolute maximum current the transistor can push through the circuit before it saturates.

How it comes about: If we take our AC voltage equation ($v_{ce}=-i_c\cdot r_c$) and substitute the total current and voltage equations from Step 1, we get the fundamental AC load line equation: $v_{CE}-V_{CEQ}=-(i_C-I_{CQ})\cdot r_c$

To find the saturation point (the Y-axis intercept), we want to know the maximum current when the voltage across the transistor drops to zero. So, we set $v_{CE}=0$: $0-V_{CEQ}=-(I_{C(sat)}-I_{CQ})\cdot r_c$ $-V_{CEQ}=-I_{C(sat)}\cdot r_c+I_{CQ}\cdot r_c$ Dividing everything by $r_c$ and rearranging to solve for $I_{C(sat)}$ gives you your slide’s equation: $I_{C(sat)}=I_{CQ}+\frac{V_{CEQ}}{r_c}$

4. Deriving $V_{CE(off)}$ (The X-axis Intercept / Cutoff Point)

The equation $V_{CE(off)}=V_{CEQ}+I_{CQ}\cdot r_c$ determines the absolute maximum voltage across the transistor before the AC signal is completely cut off.

How it comes about: We use the exact same fundamental equation: $v_{CE}-V_{CEQ}=-(i_C-I_{CQ})\cdot r_c$

To find the cutoff point (the X-axis intercept), we want to know the maximum voltage when the collector current drops entirely to zero. So, we set $i_C=0$: $V_{CE(off)}-V_{CEQ}=-(0-I_{CQ})\cdot r_c$ $V_{CE(off)}-V_{CEQ}=I_{CQ}\cdot r_c$ Rearranging to solve for $V_{CE(off)}$ gives you your slide’s equation: $V_{CE(off)}=V_{CEQ}+I_{CQ}\cdot r_c$

5. Putting it all together

The final two equations you mentioned simply take the formulas for $I_{C(sat)}$ and $V_{CE(off)}$ and swap out $r_c$ for the actual resistor values of your specific circuit ($R_C//R_1$).

Therefore, the extreme endpoints of your AC load line are:

• $I_{C(sat)}=I_{CQ}+\frac{V_{CEQ}}{R_C//R_1}$
• $V_{CE(off)}=V_{CEQ}+I_{CQ}\cdot (R_C//R_1)$

What this means for you: When you are asked to draw an AC load line in your exam, you will calculate these two exact values. You will put a dot on the Y-axis at $I_{C(sat)}$, a dot on the X-axis at $V_{CE(off)}$, and draw a steep straight line connecting them. This line will perfectly pass through your DC Q-point, showing you exactly how large your AC signal can swing before it gets clipped.

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ASCII Diagram of AC Load Line vs. DC Load Line

I_C (collector current)
^        |
|        |
|        * AC load line (steeper)
|       /
|      / \
|     /   \    (Q is center)
| DC /-----Q------\  <-- DC Load Line
|   /      |      \
|  *       |       \
|__________|_________>  V_CE (collector-emitter voltage)
Vce(off)   Q      Vce(sat)

• Q = Quiescent (DC) point.
• AC load line = swing region; endpoints are calculated using formulas above.
• Swing too far? Clipping/distortion.

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Practical Exam/Lab Tips

• Always substitute actual resistor values into formulas for $r_c$: R_C // R_L where $R_L$ is the AC load.
• Use the calculated Q-point as the center of your AC load line sketch.
• Show endpoints clearly; label axes and units.
• Remember: The slope of the AC load line is $-1/(R_C//R_L)$

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Quick Summary Box

• AC load line = swing limits.
• Get endpoints:
  • $I_{C(sat)}=I_{CQ}+\frac{V_{CEQ}}{R_C//R_L}$
  • $V_{CE(off)}=V_{CEQ}+I_{CQ}\cdot (R_C//R_L)$
• Use Q-point for max signal.
• Draw straight line connecting these ends, passing through Q.
• Exceeding these limits? Expect distortion!

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